The Challenge of Hardware Verification

Hardware verification is a critical bottleneck in chip design, often consuming the majority of the development cycle. The primary difficulty lies in generating testbench stimuli that achieve high functional coverage—ensuring that all corner cases and logic paths of a design are exercised. Traditional constrained-random verification often struggles to hit complex, deep-state coverage goals, while single-model AI generation frequently suffers from mode collapse, where the model repeatedly generates similar, "easy" test cases rather than exploring the full state space.

The CHORUS Framework: Leveraging Complementary Experts

CHORUS (Complementary Experts for High-Coverage Testbench Stimulus Generation) addresses this by moving away from a monolithic generation approach. Instead, it employs a committee of specialized "experts." Each expert in the CHORUS framework is trained or prompted to focus on different aspects of the design's functionality or different coverage metrics.

By maintaining a diverse set of experts, the system ensures that the generated stimuli are not only varied but also specifically targeted at hard-to-reach coverage points. The framework uses a coordination mechanism to select or combine the outputs of these experts, ensuring that the testbench remains valid while maximizing the breadth of the verification space. This approach effectively mitigates the risk of the model getting stuck in a local optimum of "safe" but low-value test cases.

Impact on Coverage and Efficiency

By distributing the generation task across complementary models, CHORUS achieves significantly higher functional coverage compared to baseline methods. The framework allows for more efficient exploration of the design's state space, reducing the time required to reach verification closure. This modular approach also makes the system more maintainable; as new coverage requirements emerge, new experts can be added to the ensemble without needing to retrain the entire system from scratch. The research demonstrates that this multi-expert strategy is essential for handling the increasing complexity of modern hardware designs, where single-model solutions fail to provide sufficient verification depth.